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PLL102-109中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書
PLL102-109規(guī)格書詳情
DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVDD to ground.
FEATURES
? PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
? Distributes one clock Input to one bank of six differential outputs.
? Track spread spectrum clocking for EMI reduction.
? Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled.
? Two independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ±100ps.
? Support 2-wire I2C serial bus interface.
? 2.5V Operating Voltage.
? Available in 28-Pin 209mil SSOP.
產(chǎn)品屬性
- 型號：
PLL102-109
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Programmable DDR Zero Delay Clock Driver
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
PHASELINK |
22+23+ |
SSOP |
36452 |
絕對原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
PHASELINK |
23+ |
SSOP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
PHASELIN |
0350+ |
SSOP48 |
30 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) | ||
PLL |
23+ |
SSOP |
360000 |
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價(jià)格優(yōu)勢、品種 |
詢價(jià) | ||
ZCOMM |
24+ |
SMD |
1680 |
ZCOMM專營品牌進(jìn)口原裝現(xiàn)貨假一賠十 |
詢價(jià) | ||
PHASELI |
2020+ |
SSOP48 |
8000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) | ||
PHASELIN |
22+ |
SSOP48 |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價(jià) | ||
KHATOD |
20+ |
光電元件 |
982 |
就找我吧!--邀您體驗(yàn)愉快問購元件! |
詢價(jià) | ||
PHASELIN |
0350+ |
SSOP48 |
30 |
普通 |
詢價(jià) | ||
PHASELINK |
23+ |
SSOP |
8890 |
價(jià)格優(yōu)勢/原裝現(xiàn)貨/客戶至上/歡迎廣大客戶來電查詢 |
詢價(jià) |
