PLL102-05中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書
PLL102-05規(guī)格書詳情
DESCRIPTION
The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
? Frequency range 25 ~ 60MHz.
? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
? Zero input - output delay.
? Less than 700 ps device - device skew.
? Less than 250 ps skew between outputs.
? Less than 150 ps cycle - cycle jitter.
? Output Enable function tri-state outputs.
? 3.3V operation.
? Available in 8-Pin 150mil SOIC.
產(chǎn)品屬性
- 型號：
PLL102-05
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Low Skew Output Buffer
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
Phaselink |
06+08+ |
SOIC8 |
364 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
PHASELIN |
24+ |
NA/ |
30 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
A/N |
1715+ |
SOP |
251156 |
只做原裝正品現(xiàn)貨假一賠十! |
詢價 | ||
23+ |
BGAQFP |
8659 |
原裝公司現(xiàn)貨!原裝正品價格優(yōu)勢. |
詢價 | |||
PHASELINK |
25+23+ |
SSOP |
36452 |
絕對原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價 | ||
PLL |
23+ |
SOP |
9365 |
價格優(yōu)勢/原裝現(xiàn)貨/客戶至上/歡迎廣大客戶來電查詢 |
詢價 | ||
PHASELINK |
23+ |
SOP |
18509 |
一級代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價 | ||
PHASELINK |
24+ |
SSOP |
2987 |
只售原裝自家現(xiàn)貨!誠信經(jīng)營!歡迎來電! |
詢價 | ||
Phaselink |
23+ |
SOIC8 |
12800 |
##公司主營品牌長期供應(yīng)100%原裝現(xiàn)貨可含稅提供技術(shù) |
詢價 | ||
PHASELINK |
22+ |
SOIC8 |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價 |
