CYP15G0402DXB-BGC集成電路（IC）的電信規(guī)格書PDF中文資料

Functional Description

The CYP(V)15G0402DXB[1] Quad HOTLink II? SERDES is a point-to-point communications building block allowing the transfer of preencoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link.

Features

? Second-generation HOTLink? technology

? Compliant to multiple standards

— Fibre Channel, Gigabit Ethernet (IEEE802.3z), ESCON? and DVB-ASI

— CYV15G0402DXB compliant to SMPTE 259M and SMPTE 292M

? Quad-channel transceiver operates from 195 to 1500 Mbps serial data rate

— Aggregate throughput of 12 Gbps

? 10-bit unencoded data transport

? Selectable parity check/generate

? Four independent 10-bit channels with separate Clock and Data Recovery for each channel

? Selectable input clocking options

? MultiFrame? Receive Framer

— Comma or full K28.5 detect

— Single or Multi-Byte framer for byte alignment

— Low-latency option

? Synchronous LVTTL parallel interface

? Internal phase-locked loops (PLLs) with no external PLL components

? Optional Phase Align Buffer in Transmit Path

? Differential PECL-compatible serial inputs

? Differential PECL-compatible serial outputs

— Source matched for 50? transmission lines

— No external resistors required

— Signaling rate controlled edge rates

? Compatible with

— Fiber-optic modules

— Copper cables

— Circuit board traces

? JTAG boundary scan

? Built-In Self-Test (BIST) for at-speed link testing

? Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

? Low-power 2.5W @3.3V typical

? Single 3.3V supply

? 256-ball thermally enhanced BGA

? Pb-Free package option available

? 0.25μ BiCMOS technology