AD9552BCPZ-REEL7集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

AD9552BCPZ-REEL7屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9552BCPZ-REEL7時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

GENERAL DESCRIPTION

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.

FEATURES

Converts a low frequency input reference signal to a high

frequency output signal

Input frequencies from 6.6 MHz to 112.5 MHz

Output frequencies up to 900 MHz

Preset pin programmable frequency translation ratios

Arbitrary frequency translation ratios via SPI port

On-chip VCO

Accepts a crystal resonator and/or an external oscillator

as a reference frequency source

Secondary output (either integer-related to the primary

output or a copy of the reference input)

RMS jitter: <0.5 ps

SPI-compatible, 3-wire programming interface

Single supply (3.3 V)

Very low power: <400 mW (under most conditions)

Small package size (5 mm × 5 mm)

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Extremely flexible frequency translation with low jitter for

SONET/SDH (including FEC), 10 Gb Ethernet, Fibre

Channel, and DRFI/DOCSIS

High-definition video frequency translation

Wireless infrastructure

Test and measurement (including handheld devices)