GENERAL DESCRIPTION

The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input.

FEATURES

Converts preset standard input frequencies to standard

output frequencies

Input frequencies from 8 kHz to 200 MHz

Output frequencies up to 810 MHz LVPECL and LVDS

(200 MHz CMOS)

Preset pin-programmable frequency translation ratios

On-chip VCO

Single-ended CMOS reference input

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer

and tolerance specifications

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Flexible frequency translation for wireline applications such

as Ethernet, T1/E1, SONET/SDH, GPON, xDSL

Wireless infrastructure

Test and measurement (including handheld devices)

AD9550屬于集成電路（IC） > 應用特定時鐘/定時。亞德諾半導體技術有限公司制造生產的AD9550應用特定時鐘/定時專用時鐘和計時 IC（集成電路）產品族中的產品主要用于執(zhí)行與時間或頻率信息生成和分配相關的各種操作，適合的設計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設備、藍光光盤播放器、以太網設備、PCIe、SATA、光纖通道接口、車載娛樂總線等。