General Description

The Micron? 256Mb reduced latency DRAM (RLDRAM?) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.

RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc.

Features

? Organization 8 Meg x 32, 16 Meg x 16 in 8 banks

? Cyclic bank addressing for maximum data bandwidth

? Non multiplexed addresses

? Non interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR

? Up to 600 Mb/sec/pin data rate

? Programmable READ latency (RL) of 5-6

? Data valid signal (DVLD) activated as read data is available

? Data mask signals (DM0/DM1) to mask first and

? second part of write data burst

? IEEE 1149.1 compliant JTAG boundary scan

? 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O

? Pseudo-HSTL 1.8V I/O Supply

? Internal auto precharge

? Refresh requirements: 32ms at 95°C case

temperature (8K refresh for each bank, 64K refresh

command must be issued in total each 32ms)

? 144-pin, 11mm x 18.5mm μBGA package