M48Z512A-70CS1中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The M48Z512A/Y/V ZEROPOWER? RAM is a non-volatile, 4,194,304-bit static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module.

Features

■ Integrated, ultra low power SRAM, power-fail control circuit, and battery

■ Conventional SRAM operation; unlimited WRITE cycles

■ 10 years of data retention in the absence of power

■ Automatic power-fail chip deselect and WRITE protection

■ Two WRITE protect voltages:

(VPFD = power-fail deselect voltage)

– M48Z512A: VCC = 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

– M48Z512AY: VCC = 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

– M48Z512AV: VCC = 3.0 to 3.6 V;

2.8 V ≤ VPFD ≤ 3.0 V

■ Battery internally isolated until power is applied

■ Pin and function compatible with JEDEC standard 512 K x 8 SRAMs

■ PMDIP32 is an ECOPACK? package

■ RoHS compliant

– Lead-free second level interconnect