M48Z512A集成電路（IC）的存儲(chǔ)器規(guī)格書(shū)PDF中文資料

M48Z512A屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M48Z512A存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

Description

The M48Z512A/Y/V ZEROPOWER? RAM is a non-volatile, 4,194,304-bit static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module.

Features

■ Integrated, ultra low power SRAM, power-fail control circuit, and battery

■ Conventional SRAM operation; unlimited WRITE cycles

■ 10 years of data retention in the absence of power

■ Automatic power-fail chip deselect and WRITE protection

■ Two WRITE protect voltages:

(VPFD = power-fail deselect voltage)

– M48Z512A: VCC = 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

– M48Z512AY: VCC = 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

– M48Z512AV: VCC = 3.0 to 3.6 V;

2.8 V ≤ VPFD ≤ 3.0 V

■ Battery internally isolated until power is applied

■ Pin and function compatible with JEDEC standard 512 K x 8 SRAMs

■ PMDIP32 is an ECOPACK? package

■ RoHS compliant

– Lead-free second level interconnect