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ICSSSTUAF32866BHLFT中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

ICSSSTUAF32866BHLFT
廠(chǎng)商型號(hào)

ICSSSTUAF32866BHLFT

功能描述

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

文件大小

640.03 Kbytes

頁(yè)面數(shù)量

31 頁(yè)

生產(chǎn)廠(chǎng)商 Integrated Device Technology, Inc.
企業(yè)簡(jiǎn)稱(chēng)

IDT

中文名稱(chēng)

Integrated Device Technology, Inc.官網(wǎng)

原廠(chǎng)標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠(chǎng)下載

更新時(shí)間

2024-12-26 19:21:00

ICSSSTUAF32866BHLFT規(guī)格書(shū)詳情

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low.

Features

? 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality

? Supports SSTL_18 JEDEC specification on data inputs and outputs

? Supports LVCMOS switching levels on C0, C1, and RESET inputs

? Low voltage operation: VDD = 1.7V to 1.9V

? Available in 96-ball LFBGA package

Applications

? DDR2 Memory Modules

? Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

? Ideal for DDR2 667 and 800

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