ICSS98UAE877AKLF中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Low skew, low jitter PLL clock driver

? 1 to 10 differential clock distribution

? Feedback pins for input to output synchronization

? Spread Spectrum tolerant inputs

? Auto PD when input signal is at a certain logic state

? Available in 52-ball VFBGA and a 40-pin MLF

Applications

? DDR2 Memory Modules / Zero Delay Board Fan Out

? Provides complete DDR DIMM solution with

IDT74SSTUAE32xxx family

Switching Characteristics

? Period jitter: 40ps (DDR2-400/533)

30ps (DDR2-667)

? Half-period jitter: 60ps (DDR2-400/533)

50ps (DDR2-667)

? Output-Output Skew 40ps (DDR2-400/533)

30ps (DDR2-667)

? Cycle-Cycle Jitter 40ps