HD74HCT564中文資料日立數(shù)據(jù)手冊PDF規(guī)格書

Description

These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and HD74HCT574 is only that the former has inverting outputs and the latter has non-inverting outputs.

Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features

? LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

? High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)

? High Output Current: Fanout of 15 LSTTL Loads

? Wide Operating Voltage: VCC = 4.5 to 5.5 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)