DSP56311VF150集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

The DSP56311 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. The onboard EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolution based algorithms.

The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power.

Features

High-Performance DSP56300 Core

? Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O

? Object code compatible with the DSP56000 core with highly parallel instruction set

? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control

? Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memory expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

? Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two- , and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals

? Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination

? Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG) test access port (TAP)

Enhanced Filter Coprocessor (EFCOP)

? Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

? Operation at the same frequency as the core (up to 150 MHz)

? Support for a variety of filter modes, some of which are optimized for cellular base station applications:

? Real finite impulse response (FIR) with real taps

? Complex FIR with complex taps

? Complex FIR generating pure real or pure imaginary outputs alternately

? A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

? Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

? Direct form 2 (DFII) IIR filter

? Four scaling factors (1, 4, 8, 16) for IIR output

? Adaptive FIR filter with true least mean square (LMS) coefficient updates

? Adaptive FIR filter with delayed LMS coefficient updates

Internal Peripherals

? Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

? Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)

? Serial communications interface (SCI) with baud rate generator

? Triple timer module

? Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled