1. General description

The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate

up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state

synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed

while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held

HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee

predictable behavior. The device can be cleared at any time by the asynchronous master reset

input (MR). It may also be loaded in parallel by activating the asynchronous parallel load input (PL).

The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When

the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU

causes TCU to go LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up

clock. Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD goes

LOW. The terminal count outputs duplicate the clock waveforms and can be used as the clock input

signals to the next higher-order circuit in a multistage counter. Multistage counters are not fully

synchronous, since there is a slight delay time difference added for each stage that is added. The

counter may be preset by the asynchronous parallel load capability of the circuit. Information on the

parallel data inputs (D0 to D3), is loaded into the counter. This information appears on the outputs

(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.

A HIGH level on the master reset (MR) input disables the parallel load gates. It overrides both clock

inputs and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a

reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a legitimate

signal and it is counted. Inputs include clamp diodes that enable the use of current limiting resistors

to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 2.0 to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Input levels:

? For 74HC193-Q100: CMOS level

? For 74HCT193-Q100: TTL level

? Synchronous reversible 4-bit binary counting

? Asynchronous parallel load

? Asynchronous reset

? Expandable without external logic

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

74HC193PW-Q100屬于集成電路（IC） > 計(jì)數(shù)器，除法器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74HC193PW-Q100計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。