Features

? CPU subsystem

- One or two[1] 250-MHz 32-bit Arm? Cortex?-M7 CPUs, each with

? Single-cycle multiply

? Single/double-precision floating point unit (FPU)

? 16-KB data cache, 16-KB instruction cache

? Memory Protection Unit (MPU)

? 16-KB instruction and 16-KB data Tightly-Coupled Memories (TCM)

- 100-MHz 32-bit Arm? Cortex? M0+ CPU with

? Single-cycle multiply

? MPU

- Inter-processor communication in hardware

- Three DMA controllers

? Peripheral DMA controller #0 (P-DMA0, DW0) with 100 channels

? Peripheral DMA controller #1 (P-DMA1, DW1) with 58 channels

? Memory DMA controller (M-DMA0, DMAC0) with 8 channels

? Integrated memories

- Up to 4160 KB of code-flash with an additional up to 256 KB of work-flash

? Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

? Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

? Flash programming through SWD/JTAG interface

- Up to 768 KB of SRAM with selectable retention granularity

? Cryptography engine

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

? Using digital signature verification

? Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

? Safety for application

- Memory Protection Unit (MPU)

- Shared Memory Protection Unit (SMPU)

- Peripheral Protection Unit (PPU)

- Watchdog Timer (WDT)

- Multi-Counter Watchdog Timer (MCWDT)

- Low-Voltage Detector (LVD)

- Brown-Out Detection (BOD)

- Overvoltage Detection (OVD)

- Clock Supervisor (CSV)

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

? Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

? Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA

? One threshold level (1.1 V) for BOD on VCCD

? Wakeup

- Up to two pins to wake from Hibernate mode

- Up to 220 GPIO pins to wake from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

? Clocks

- Internal Main Oscillator (IMO)

- Internal Low-Speed Oscillator (ILO)

- External Crystal Oscillator (ECO)

- Watch Crystal Oscillator (WCO)

- Phase-Locked Loop (PLL)

- Frequency-Locked Loop (FLL)

? Communication interfaces

- Up to eight CAN FD channels

? Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

? Compliant with ISO 11898-1:2015

? Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

? ISO 16845:2015 certificate available

- Up to 11 runtime-reconfigurable serial communication block (SCB) channels, each configurable as I2C, SPI,

or UART

- One 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw

? Supports the following PHY interfaces:

Media-independent interface (MII)

Reduced media-independent interface (RMII)

? Compliant with IEEE-802.1BA Audio Video Bridging (AVB)

? Compliant with IEEE-1588 Precision Time Protocol (PTP)

? External memory interface

- One SPI (Single, Dual, Quad, or Octal) or HYPERBUS? interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

? SDHC interface

- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure

Digital (SD), or Secure Digital Input Output (SDIO)

? Compliant with eMMC 5.1, SD 6.0, and SDIO 4.10 specifications

- Data rates up to SD High Speed 50 MHz, or eMMC 52-MHz DDR

? Audio interface

- Three Inter-IC Sound (I2S) Interface for connecting digital audio devices

- I2S, left justified, or Time Division Multiplexed (TDM) audio formats

- Independent transmit or receive operation, each in master or slave mode

? Timers

- Up to 75 16-bit and eight 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks

? Up to 12 16-bit counters for motor control

? Up to 63 16-bit counters and eight 32-bit counters for regular operations

? Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time

(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

? Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

? Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- 12- and 24-hour formats

- Automatic leap-year correction

? I/O

- Up to 220 programmable I/Os

- Three I/O types

? GPIO Standard (GPIO_STD)

? GPIO Enhanced (GPIO_ENH)

? High-Speed I/O Standard (HSIO_STD)

? Regulators

- Generate a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Three regulators:

? DeepSleep

? Core internal

? Core external

? Programmable analog

- Three SAR A/D converters with up to 75 external channels (72 I/Os + 3 I/Os for motor control)

? ADC0 supports 32 logical channels, with 32 + 1 physical connections

? ADC1 supports 32 logical channels, with 32 + 1 physical connections

? ADC2 supports 8 logical channels, with 8 + 1 physical connections

? Any external channel can be connected to any logical channel in the respective SAR

- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps

- Each ADC also supports six internal analog inputs like

? Bandgap reference to establish absolute voltage levels

? Calibrated diode for junction temperature calculations

? Two AMUXBUS inputs and two direct connections to monitor supply levels

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels

- Synchronized sampling of all ADCs for motor-sense applications

? Smart I/O

- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os

- Up to 36 I/Os (GPIO_STD) supported

? Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm? Serial Wire Debug (SWD) port

- Supports Arm? Embedded Trace Macrocell (ETM) Trace

? Data trace using SWD

? Instruction and data trace using JTAG

? Industry advanced development tools

- Infineon IDE ModusToolbox? software for code development and debugging

? Packages

- 100-TEQFP, 14 × 14 × 1.6 mm (max), 0.5-mm lead pitch

- 144-TEQFP, 20 × 20 × 1.6 mm (max), 0.5-mm lead pitch

- 176-TEQFP, 24 × 24 × 1.6 mm (max), 0.5-mm lead pitch

- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch