VSC8115YA中文資料VITESSE數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Description

The VSC8115 functions as a clock and data recovery unit for SONET/SDH-based equipment to derive high speed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s (STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed using an output flip-flop. Both recovered clock and retimed data outputs can be configured as LVDS or LVPECL signals to facilitate a low-jitter and low power interface.

Features

? Performs clock and data recovery for 622.08Mb/s (STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1) NRZ data

? Meets Bellcore, ITU and ANSI Specifications for Jitter Performance

? 19.44MHz reference frequency LVTTL Input

? Lock Detect output pin monitors data run length and frequency drift from the reference clock

? Data is Retimed at the Output

? Active High Signal Detect LVPECL Input

? Low-jitter high speed outputs can be configured as either LVPECL or low power LVDS

? Low power - 0.188 Watts Typical Power

? +3.3V Power Supply

? 20 Pin TSSOP Package

? Requires One External Capacitor

? PLL bypass operation facilitates the board debug process