VSC6250中文資料VITESSE數(shù)據(jù)手冊(cè)PDF規(guī)格書

General Description

The VSC6250 is intended for use in the next generation of high-speed, high-accuracy memory testers for devices such as Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, and fast SSRAM.

The VSC6250 provides ultra-precise timing to allow next generation memory testers to achieve excellent overall timing accuracy. Timing delays of the VSC6250 are extremely stable with respect to temperature and voltage. Proprietary circuit design and process technology reduce pattern, data, frequency, and duty-cycle dependencies to an absolute minimum. The VSC6250 requires no external DACs, which eliminates errors due to DAC reference noise and analog crosstalk, and DAC temperature and voltage drift. The VSC6250 is available in a 128-pin PQFP, 14x20mm thermally-enhanced package.

Features

? High-Speed Operation:

1 Gb/s Data Rate

500ps min Output Pulse Width

750ps min Input Pulse Width

? Excellent Overall Timing Accuracy:

Ultra-Stable Timing Delays

Minimum Pattern Dependence

Very Fine Timing Resolution (1 LSB = 8ps)

? High Level of Integration Reduces Board Area:

16 Independently Adjustable Delay Lines in a

Single Package

? Configurable as 2 1:8 or 1:16

? Wide Span: > 4ns Usable Range

? Pulse Width Adjustment to Compensate for

Dispersion in Pin Electronics:

± 2ns Independent Adjustment of Rising and

Falling Edges

? Fully Digital Single-Chip Solution:

No Off-Chip DACs Required

No DAC-Induced Timing Errors from Analog

Crosstalk, Reference Noise, Temperature, or

Voltage Drift

? Single Power Supply: -2V @ 5W

? 128-Pin PQFP, 14x20mm Thermally-Enhanced Package

Applications

? Drive-Side Deskew in High-Speed Memory

Testers

? Direct RAMBUS DRAM, SLDRAM, DDR

SDRAM, Fast SSRAM

? High-Speed Instrumentation: Pulse Generators,

Timing Margin Testers for Datalink, Interface,

and Disk Drive Applications

? Telecom, Datacom, and Computer Deskew