V103YLF集成電路（IC）的驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

General Description

The V103 LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions and can be used in Plasma, Rear Projector, Front Projector, CRT and LCD display applications. It can also be used in other high-bandwidth parallel data applications and provides a low EMI interconnect over a low cost, low bus width cable up to several meters in length.

Features

? Pin compatible with THine THC63LVD103

? Wide pixel clock range: 8 - 135 MHz

? Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P

? Internal PLL requires no external loop filter

? Selectable rising or falling clock edge for data alignment

? Compatible with Spread Spectrum clock source

? Reduced LVDS output voltage swing mode (selectable) to minimize EMI

? CMOS/TTL data inputs can be configured for reduced input voltage swing

? Single 3.3 V supply

? Low power consumption CMOS design

? Power down mode

? 64-pin TQFP lead free package