UT8CR512K32-17VWC中文資料AEROFLEX數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

INTRODUCTION

The UT8CR512K32 is a high-performance CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 words by 8 bit SRAMs with common output enable. Easy memory expansion is provided by active LOW chip enables (En), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90 when deselected.

Writing to each memory is accomplished by taking the corresponding chip enable (En) input LOW and write enable (Wn) input LOW. Data on the I/O pins is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking the chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die.

FEATURES

? 17ns maximum access time

? Asynchronous operation for compatibility with industry standard 512K x 8 SRAMs

? CMOS compatible inputs and output levels, three-state bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

? Operational environment:

- Intrinsic total-dose: 300 krad(Si)

- SEL Immune >100 MeV-cm2/mg

- LETth (0.25): 53.0 MeV-cm2/mg

- Memory Cell Saturated Cross Section 1.67E-7cm2/bit

- Neutron Fluence: 3.0E14n/cm2

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup 1.0E11 rad(Si)/sec

? Packaging options:

- 68-lead ceramic quad flatpack (20.238 grams with lead frame)

? Standard Microcircuit Drawing 5962-04227

- QML Q & V compliant part