UPD77018中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

FEATURES

? FUNCTIONS

? Instruction cycle: 30 ns (MIN.)

Operation clock: 33 MHz

External clock: 33, 16.5, 8.25, 4.125 MHz

Crystal: 33 MHz

? On-chip PLL to provide higher operation clock than the external clock

? Dual load/store

? Hardware loop function

? Conditional execution

? Executes product-sum operation in one instruction cycle

? PROGRAMMING

? 16 bits ′ 16 bits + 40 bits ? 40 bits multiply accumulator

? 8 general registers (40 bits each)

? 8 ROM/RAM data pointer: each data memory area has 4 registers

? 10 source interrupts (external: 4, internal: 6)

? 3 operand instructions (example: R0 = R0 +R1L*R2L)

? Nonpipeline on execution stage

? MEMORY AREAS

? Instruction memory area : 64K words ′ 32 bits

? Data memory areas : 64K words ′ 16 bits ′ 2 (X memory, Y memory)