UPD178023中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

· High-capacity ROM and RAM

· Instruction cycle:

0.45/0.89/1.78/3.56/7.11 ms (with crystal resonator of

fX = 4.5 MHz)

· Many internal hardware units

General-purpose I/O ports, A/D converter, serial

interface (I2C bus and UART mode), timers, frequency

counter, power-ON clear circuit

· Hardware for PLL frequency synthesizer

Dual modulus prescaler, programmable divider,

phase comparator, charge pump

· Vectored interrupt sources: 17

· Supply voltage

:VDD = 4.5 to 5.5 V (during PLL and CPU operations)

:VDD = 3.5 to 5.5 V (during CPU operation)