TS83102G0BCGL中文資料愛特梅爾數(shù)據(jù)手冊PDF規(guī)格書

Description

The TS83102G0B is a monolithic 10-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. It uses an innovative architecture, including an on-chip Sample and Hold (S/H). The 3.3 GHz full power input bandwidth and band flatness performances enable the digitizing of high IF and large bandwidth signals.

Features

? Up to 2 Gsps Sampling Rate

? Power Consumption: 4.6 W

? 500 mVpp Differential 100 ? or Single-ended 50 ? (±2 ) Analog Inputs

? Differential 100 ? or Single-ended 50 ? Clock Inputs

? ECL or LVDS Output Compatibility

? 50 ? Differential Outputs with Common Mode not Dependent on Temperature

? ADC Gain Adjust

? Sampling Delay Adjust

? Offset Control Capability

? Data Ready Output with Asynchronous Reset

? Out-of-range Output Bit

? Selectable Decimation by 32 Functions

? Gray or Binary Selectable Output Data; NRZ Output Mode

? Pattern Generator Output (for Acquisition System Monitoring)

? Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)

? CBGA 152 Cavity Down Hermetic Package

? CBGA Package Evaluation Board TSEV83102G0BGL

? Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0

Performance

? 3.3 GHz Full Power Input Bandwidth (-3 dB)

? Gain Flatness: ± 0.2 dB (from DC up to 1.5 GHz)

? Low Input VSWR: 1.2 Max from DC to 2.5 GHz

? SFDR = -59 dBc; 7.6 Effective Bits at FS = 1.4 Gsps, FIN = 700 MHz [-1 dBFS]

? SFDR = -53 dBc; 7.1 Effective Bits at Fs = 1.4 Gsps, FIN = 1950 MHz [-1 dBFS]

? SFDR = -54 dBc; 6.5 Effective Bits at FS = 2 Gsps, FIN = 2 GHz [-1 dBFS]

? Low Bit Error Rate (10-12) at 2 Gsps

Application

? Direct RF Down Conversion

? Wide Band Satellite Receiver

? High-speed Instrumentation

? High-speed Acquisition Systems

? High-energy Physics

? Automatic Test Equipment

? Radar