TS80C54X2中文資料Temic數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

TEMIC TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C54/58X2 retains all features of the TEMIC 80C51 with extended ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C54/58X2 has a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism.

Features

● 80C52 Compatible

? 8051 pin and instruction compatible

? Four 8-bit I/O ports

? Three 16-bit timer/counters

? 256 bytes scratchpad RAM

● High-Speed Architecture

? 40 MHz @ 5V, 30MHz @ 3V

? X2 Speed Improvement capability (6 clocks/ machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)

● Dual Data Pointer

● On-chip ROM/EPROM (16K-bytes, 32K-bytes)

● Programmable Clock Out and Up/Down Timer/ Counter 2

● Hardware Watchdog Timer (One-time enabled with Reset-Out)

● Asynchronous port reset