TP2104N3中文資料SUTEX數(shù)據(jù)手冊PDF規(guī)格書

General Description

This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

Features

? High input impedance and high gain

? Low power drive requirement

? Ease of paralleling

? Low CISS and fast switching speeds

? Excellent thermal stability

? Integral source-drain diode

? Free from secondary breakdown

Applications

? Logic level interfaces - ideal for TTL and CMOS

? Solid state relays

? Analog switches

? Power management

? Telecom switches