T74LS164中文資料意法半導體數(shù)據(jù)手冊PDF規(guī)格書

■ TYPICAL SHIFT FREQUENCY OF 35 MHz

■ ASYNCHRONOUS MASTER RESET

■ GATED SERIAL DATA INPUT

■ FULLY SYNCHRONOUS DATA TRANSFERS

■ INPUT CLAMP DIODES LIMIT HIGH SPEED

TERMINATION EFFECTS

■ FULLY TTL AND CMOS COMPATIBLE

DESCRIPTION

The T74LS164 is a 8-Bit Serial-In Parallel-Out Shift

Register. Serial data is entered through a 2-Input

AND gate synchronous with LOW to HIGH transition

of the clock. The device features an asincronous

Master Reset which clears the register setting all

outputs LOW indipendent of the clock. It utilizes the

Schottky diode clamped process to archive high

sppeds and is fully compatible with all TTL roducts.