STLC5432中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

STLC5432, CMOS device, interfaces the multiplex system to the physical CEPT Transmission link at 2048Kb/s. Furthermore, thanks to its flexibility, it is the optimum solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 specifications.

STLC5432 is the real single chip solution that allows the best system flexibility and easy design. STLC5432 can work either in 2048 or 4096 or 8192 Kbit/s systems programming the CR4 register (when parallel micro interface selected).

■ ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD)

■ ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2)

■ HDB3/BIN ENCODER AND DECODER ON CHIP

■ MULTIFRAME STRUCTURE HANDLING

■ BUILT IN CRC4

■ EASY LINK TO ST5451/MK50H25/MK5027 LINK CONTROLLERS.

■ DATA RATE: 2048, 4096 AND 8192 Kb/s FOR MULTIPLEXED APPLICATIONS

■ FOUR LOOPBACK MODES FOR TESTING

■ PSEUDO RANDOM SEQUENCE GENERATOR AND ANALYZER FOR ON-LINE, OFFLINE AND AUTOTEST

■ CLOCK RECOVERY CIRCUITRY ON CHIP

■ 64 BYTE ELASTIC MEMORY FOR TIME COMPENSATION AND AUTOMATIC FRAME AND SUPERFRAME ALIGNMENT

■ 32 ON CHIP REGISTERS FOR CONFIGURATIONS, TESTING, ALARMS, FAULT AND ERROR RATE CONTROL.

■ AUTO ADAPTATIVE DETECTION THRESHOLD

■ AUTOMATIC EQUALIZER OPTION

■ 5V POWER SUPPLY

■ AMI OR HDB3 CODE SELECTION

■ PARALLEL OR SERIAL MICROPROCESSOR INTERFACE OPTION

■ BOTH μp AND STAND ALONE MODE AVAILABLE