首頁(yè) >SSTUB32868ET/G-T>規(guī)格書列表
零件編號(hào) | 下載 訂購(gòu) | 功能描述/絲印 | 制造商 上傳企業(yè) | LOGO |
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28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2CONFIDENTIAL Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2CONFIDENTIAL Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT |
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