1 Features

? AEC-Q100 qualified for automotive applications:

– Device temperature grade 1:

? 40°C to + 125°C, TA

– Device HBM ESD Classifiaction Level 2

– Device CDM ESD Classifcation Level C6

? Available in wettable flank QFN (WRKS) package

? 2 V to 5.5 V VCC operation

? Maximum tpd of 10.5 ns at 5 V

? Supports mixed-mode voltage operation on all

ports

? Ioff supports partial-power-down mode operation

? Latch-up performance exceeds 250 mA per JESD

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2 Applications

? Synchronize digital signals to clock

? Use fewer inputs to monitor signals

? Convert a switch to a toggle

3 Description

The SN74LV273A-Q1 device is an octal positive-edge

triggered D-type flip-flop with shared direct active low

clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup

time requirements is transferred to the (Q) outputs

on the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not related directly to the transition time of

the positive-going pulse. When CLK is at either the

high or low level or transitioning from a high level

to a low level, the D input has no effect at the

output. Information at the data (Q) outputs can be

asynchronously cleared with a low level input through

the clear (CLR) pin.

SN74LV273A屬于集成電路（IC） > 觸發(fā)器。美國(guó)德州儀器公司制造生產(chǎn)的SN74LV273A觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。