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SN74LS374MEL中文資料安森美半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

SN74LS374MEL
廠商型號(hào)

SN74LS374MEL

功能描述

Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output

文件大小

98.85 Kbytes

頁(yè)面數(shù)量

8 頁(yè)

生產(chǎn)廠商 ON Semiconductor
企業(yè)簡(jiǎn)稱(chēng)

ONSEMI安森美半導(dǎo)體

中文名稱(chēng)

安森美半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-27 22:58:00

SN74LS374MEL規(guī)格書(shū)詳情

Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output

The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.

The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.

?Eight Latches in a Single Package

?3-State Outputs for Bus Interfacing

?Hysteresis on Latch Enable

?Edge-Triggered D-Type Inputs

?Buffered Positive Edge-Triggered Clock

?Hysteresis on Clock Input to Improve Noise Margin

?Input Clamp Diodes Limit High Speed Termination Effects

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TI
2016+
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9000
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2020+
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80000
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MOT
23+
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20000
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TMS
23+
NA
22879
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TI
22+
DIP20
24185
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TI
5
240
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TI
22+
DIP
3000
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168
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24+
378
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17+
6200
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