SN74AS373DWR集成電路（IC）的鎖存器規(guī)格書PDF中文資料

SN74AS373DWR屬于集成電路（IC）的鎖存器。由德州儀器制造生產(chǎn)的SN74AS373DWR鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

* Eight Latches in a Single Package

* 3-State Bus-Driving True Outputs

* Full Parallel Access for Loading

* Buffered Control Inputs

* pnp Inputs Reduce dc Loading on Data

Lines

description

These octal transparent D-type latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low) or a high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and the increased drive

provide the capability to drive bus lines without

interface or pullup components.

OE does not affect internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are off.