SN74ALS373ADWR集成電路（IC）的鎖存器規(guī)格書PDF中文資料

* Eight Latches in a Single Package

* 3-State Bus-Driving True Outputs

* Full Parallel Access for Loading

* Buffered Control Inputs

* pnp Inputs Reduce dc Loading on Data

Lines

description

These octal transparent D-type latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low) or a high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and the increased drive

provide the capability to drive bus lines without

interface or pullup components.

OE does not affect internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are off.