SN74AHCT125NSR集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

1 Features

? Inputs are TTL-voltage compatible

? Latch-up performance exceeds 250 mA

per JESD 17

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Debounce a switch

? Eliminate slow or noisy input signals

3 Description

The ’AHCT125 devices are quadruple bus buffer

gates featuring independent line drivers with 3-state

outputs. Each output is disabled when the associated

output-enable (OE) input is high. When OE is low, the

respective gate passes the data from the A input to its

Y output.

For the high-impedance state during power up or

power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.