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SL74HC533D中文資料SLS數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
SL74HC533D |
| 功能描述 | Octal 3-State Inverting Transparent Latch(High-Performance Silicon-Gate CMOS) |
| 文件大小 |
57.51 Kbytes |
| 頁(yè)面數(shù)量 |
6 頁(yè) |
| 生產(chǎn)廠商 | System Logic Semiconductor |
| 企業(yè)簡(jiǎn)稱 |
SLS |
| 中文名稱 | System Logic Semiconductor官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2024-12-30 19:10:00 |
SL74HC533D規(guī)格書詳情
Octal 3-State Inverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC533 is identical in pinout to the LS/ALS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 μA
? High Noise Immunity Characteristic of CMOS Devices
產(chǎn)品屬性
- 型號(hào)：
SL74HC533D
- 制造商：
SLS
- 制造商全稱：
System Logic Semiconductor
- 功能描述：
Octal 3-State Inverting Transparent Latch(High-Performance Silicon-Gate CMOS)
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
SLS |
24+ |
SOP14 |
990000 |
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SLS |
22+ |
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12000 |
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SLS |
24+ |
SOP |
35200 |
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ST |
DIP-24 |
36900 |
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2016+ |
SOP3.9 |
6528 |
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SLS |
23+ |
SOP14 |
6850 |
只做原廠原裝正品現(xiàn)貨!假一賠十! |
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24+ |
3000 |
自己現(xiàn)貨 |
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ST |
23+ |
DIP-24 |
16900 |
正規(guī)渠道,只有原裝! |
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05+ |
原廠原裝 |
13051 |
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詢價(jià) | |||
HYNIX |
24+ |
SOP-7.2-20P |
4897 |
絕對(duì)原裝!現(xiàn)貨熱賣! |
詢價(jià) |
