SI5376B-A-BL集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書(shū)PDF中文資料

SI5376B-A-BL屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由美國(guó)思佳訊公司制造生產(chǎn)的SI5376B-A-BL時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號(hào)的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動(dòng)器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

Features

? Highly-integrated, 4 PLL clock

multiplier/jitter attenuator

? Four independent DSPLLs support

any-frequency synthesis and jitter

attenuation

? 8 inputs/8 outputs

? Each DSPLL can generate any

frequency from 2 kHz to 808 MHz

from a 2 kHz to 710 MHz input

? 350 fs rms (12 kHz– 20 MHz) and

410 fs rms (50 kHz–80 MHz)

typical

? Meets ITU-T G.8251 and Telcordia

GR-253-CORE OC-192 jitter

specifications

? Programmable loop bandwidth:

60 Hz to 8 kHz

? Faster lock acquisition compared to

the Si5374: <1.2 s

? For a very low-loop BW version, see

the Si5374

? Supports all ITU G.709 and any

custom FEC ratios (239/237,

255/238, 255/237, 255/236, 253/226)

? Integrated loop filter with

programmable bandwidth

? Simultaneous free-run and

synchronous operation

? Automatic/manual hitless input clock

switching

? Selectable output clock signal format

(LVPECL, LVDS, CML, CMOS)

? LOL and interrupt alarm outputs

? I2C programmable

? Single 1.8 V ±5 or 2.5 V ±10

operation with high PSRR on-chip

voltage regulator

? 10x10 mm PBGA