Features

? Provides jitter attenuation and frequency

translation between SONET/PDH and

Ethernet

? Supports ITU-T G.8262 Synchronous

Ethernet equipment slave clock (EEC

option 1 and 2) requirements with

optional Stratum 3 compliant timing card

clock source

? Two clock inputs/two clock outputs

? Input frequency range: 8 kHz–644 MHz

? Output frequency range: 8 kHz–644 MHz

? Ultra low jitter:

0.23 ps RMS (1.875–20 MHz)

0.47 ps RMS (12 kHz–20 MHz)

? Simple pin control interface

? Selectable loop bandwidth for jitter

attenuation: 60 to 8.4 kHz

? Automatic/Manual hitless switching

and holdover during loss of inputs

clock

? Programmable output clock signal

format: LVPECL, LVDS, CML or

CMOS

? 40 MHz crystal or XO reference

? Single supply: 1.8, 2.5, or 3.3 V

? On-chip voltage regulator with high

PSRR

? Loss of lock and loss of signal alarms

? Small size: 6 x 6 mm, 36-QFN

? Wide temperature range: –40 to

+85 oC

SI5315屬于集成電路（IC） > 應(yīng)用特定時(shí)鐘/定時(shí)。美國思佳訊公司制造生產(chǎn)的SI5315應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。