SH7105中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Overview

The SH7108 Series single-chip RISC microprocessor integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.

The SH7108 Series CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds.

Features

? Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture

- Instruction length: 16-bit fixed length for improved code efficiency

- Load-store architecture (basic operations are executed between registers)

- Sixteen 32-bit general registers

- Five-stage pipeline

- On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles

- C language-oriented 62 basic instructions

? Various peripheral functions

- Multifunction timer/pulse unit (MTU)

- Motor management timer(MMT)

- Compare match timer (CMT)

- Watchdog timer (WDT)

- Asynchronous or clocked synchronous serial communication interface (SCI)

- 10-bit A/D converter

- Clock pulse generator