SG3525AP集成電路（IC）的PMIC-穩(wěn)壓器-DCDC開關(guān)式控制器規(guī)格書PDF中文資料

SG3525AP屬于集成電路（IC）的PMIC-穩(wěn)壓器-DCDC開關(guān)式控制器。由意法半導體集團制造生產(chǎn)的SG3525APDC-DC 開關(guān)控制器PMIC（電源管理集成電路）DC 到 DC 開關(guān)式控制器是用于高效率電路的穩(wěn)壓 IC，其配置為生成高于（突升或步升）或低于（突降或步降）輸入電源的輸出電源電壓。其他拓撲結(jié)構(gòu)可能包括：降壓-升壓、反激、正激、Cuk、SEPIC、全橋、半橋和推挽式。這些器件不同于需要最小電壓并“燒盡”多余電壓的線性穩(wěn)壓器。

DESCRIPTION

The SG3525Aseries of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an under voltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includesapproximately500 mV of hysteresis for jitter free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525AoutputstagefeaturesNOR logic, giving a LOW output for an OFF state.

■ 8 TO 35 V OPERATION

■ 5.1 V REFERENCE TRIMMED TO ± 1

■ 100 Hz TO 500 KHz OSCILLATORRANGE

■ SEPARATE OSCILLATORSYNC TERMINAL

■ ADJUSTABLE DEADTIME CONTROL

■ INTERNAL SOFT-START

■ PULSE-BY-PULSESHUTDOWN

■ INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS

■ LATCHING PWM TO PREVENT MULTIPLE PULSES

■ DUAL SOURCE/SINK OUTPUT DRIVERS