S3S12HZ256J3CAA中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

The MC9S12HZ256 microcontroller units (MCU) are 16-bit devices composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B software compatible modules (MSCAN). In addition, they feature a 32x4 liquid crystal display (LCD) controller/driver, a pulse width modulator motor controller (MC) consisting of 16 high current outputs suited to drive up to four stepper motors, and four stepper stall detectors (SSD) to simultaneously calibrate the pointer position of each motor. System resource mapping, clock generation, interrupt control, and external bus interfacing are managed by the HCS12 Core. The MC9S12HZ256 have full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 8 general-purpose I/O pins are available with interrupt and wake-up capability from stop or wait mode.

Features

? HCS12 core

– 16-bit HCS12 CPU

Upward compatible with M68HC11 instruction set

Interrupt stacking and programmer’s model identical to M68HC11

16-bit ALU

Instruction queue

Enhanced indexed addressing

– MEBI (multiplexed external bus interface)

– MMC (module mapping control)

– INT (interrupt control)

– DBG (debugger and breakpoints)

– BDM (background debug mode)

? Memory

– 256K, 128K, 64K, 32K Flash EEPROM or ROM

– 2K, 1K byte EEPROM

– 12K, 6K, 4K, 2K byte RAM

? CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)

? Analog-to-digital converter

– 16 channels, 10-bit resolution

– External conversion trigger capability

? Two 1-Mbps, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation