Features

Power Supply

 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)

Clock

 Fast clock cycle time for high bandwidth

 Two input clocks (K and /K) for precise DDR timing at clock rising edges only

 Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

 Clock-stop capability with ms restart

I/O

 Separate independent read and write data ports with concurrent transactions

 100 bus utilization DDR read and write operation

 HSTL I/O

 User programmable output impedance

 PLL circuitry for wide output data valid window and future frequency scaling

 Data valid pin (QVLD) to indicate valid data on the output

Function

 Four-tick burst for reduced address frequency

 Internally self-timed write control

 Simple control logic for easy depth expansion

 JTAG 1149.1 compatible test access port

Package

 165 FBGA package (13 x 15 x 1.4 mm)