PEB20534H-52中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

Overview

The DSCC4 is a DMA Supported Serial Communication Controller with four independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications.

Features

? Serial communication controllers (SCCs)

- Four independent channels

- Full duplex data rates on each channel of up to 10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async

- Full duplex data rate of up to 52 Mbit/s on any two channels in high speed mode (HDLC: Address Mode 0 and extended transparent protocol mode); up to 45 Mbit/s on any two channels in high speed mode (HDLC: PPP modes). The aggregate bandwith for all channels is limited to 108 Mbit/s per direction.

- 17 DWORDs deep receive FIFO per SCC (+ 128 DWORDs central receive FIFO).

- 8 DWORDs deep transmit FIFO per SCC (+ 128 DWORDs central transmit FIFO).

? Serial Interface

- On chip clock generation or external clock sources

- On chip DPLLs for clock recovery

- Baud rate generator

- Clock gating signals

- Clock gapping capability

- Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1)

- NRZ, NRZI, FM and Manchester data encoding

- Optional data flow control using modem control lines (RTS, CTS, CD)

- Support of bus configuration by collision detection and resolution

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