PCK2014ADL中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The PCK2014A is a clock generator (frequency synthesizer) chip for a Pentium III and other similar processors.

The PCK2014A has six CPU clock outputs at 2.5 V, two 3V66 clocks running at 66 MHz. there are six PCI clock outputs running at 33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements.

FEATURES

? ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.

? Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA.

? Mixed 2.5 V and 3.3 V operation

? Six CPU clocks at 2.5 V

? Six PCI clocks at 3.3 V, one free-running (synchronous with CPU clocks)

? Two 3.3 V fixed clocks @ 66 MHz

? Three 2.5 V IOAPIC clocks @ 16.67 MHz

? One 3.3 V 48 MHz USB clock

? Two 3.3 V reference clocks @ 14.318 MHz

? Reference 14.31818 MHz Xtal oscillator input

? 133 MHz or 100 MHz operation

? Power management control input pins

? CPU clock jitter ≤ 150 ps cycle-cycle

? CPU clock skew ≤ 175 ps pin-pin

? 0.0 ns – 1.5 ns CPU - 3V66 delay

? 1.5 ns – 3.5 ns 3V66 - PCI delay

? 1.5 ns – 4.0 ns CPU - IOAPIC delay

? 1.5 ns – 4.0 ns CPU - PCI delay

? Available in 56-pin SSOP package

? ±0.6 Center spread spectrum capability via select pins

? –0.6 Down spread spectrum capability via select pins