P3041NSE1NNB中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

The P3041 QorIQ integrated processor utilizes four processor cores built on Power Architecture? technology. The cores include high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications.

This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design.

The chip includes the following functions and features:

? Four e500mc Power Architecture cores, each with a

backside 128 KB L2 cache with ECC

– Three levels of instructions: User, supervisor, and hypervisor

– Independent boot and reset

– Secure boot capability

? CoreNet fabric supporting coherent and non-coherent

transactions amongst CoreNet end-points

? CoreNet platform cache with ECC

? CoreNet bridges between the CoreNet fabric the I/Os,

datapath accelerators, and high and low speed peripheral

interfaces

? One 10-Gigabit Ethernet (XAUI) controller

? Five 1-Gigabit Ethernet controllers

– SGMII interfaces

— 2.5 Gbps SGMII interfaces

– RGMII interfaces

? One 64-bit DDR3 SDRAM memory controller with ECC

? Multicore programmable interrupt controller

? Four I2C controllers

? Four 2-pin UARTs or two 4-pin UARTs

? Two 4-channel DMA engines

? Enhanced local bus controller (eLBC)

? Four PCI Express 2.0 controllers/ports

? Two serial RapidIO? controllers/ports (sRIO port)

supporting version 1.3 with features from 2.1

? Two serial ATA (SATA 2.0) controllers

? Enhanced secure digital host controller (SD/MMC)

? Enhanced serial peripheral interfaces (eSPI)

? 2× high-speed USB 2.0 controllers with integrated PHYs