首頁(yè)>P2V28S40ATP-8>規(guī)格書(shū)詳情

P2V28S40ATP-8中文資料VML數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

P2V28S40ATP-8
廠商型號(hào)

P2V28S40ATP-8

功能描述

128Mb SDRAM Specification

文件大小

652.38 Kbytes

頁(yè)面數(shù)量

51 頁(yè)

生產(chǎn)廠商 Vanguard International Semiconductor
企業(yè)簡(jiǎn)稱

VML

中文名稱

Vanguard International Semiconductor官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2025-1-13 16:59:00

P2V28S40ATP-8規(guī)格書(shū)詳情

DESCRIPTION P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

FEATURES

- Single 3.3V ±0.3V power supply

- Max. Clock frequency -7:143MHz/-75:133MHz/-8:100MHz

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Byte Control- DQML and DQMU (P2V28S40ATP)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 4096 refresh cycles /64ms

- LVTTL Interface

- Package

P2V28S20ATP/30ATP/40ATP

400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

產(chǎn)品屬性

  • 型號(hào):

    P2V28S40ATP-8

  • 制造商:

    VML

  • 制造商全稱:

    VML

  • 功能描述:

    128Mb SDRAM Specification

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
MIRA
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860000
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