ORT4622集成電路（IC）的FPGA（現(xiàn)場可編程門陣列）規(guī)格書PDF中文資料

Introduction

Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT4622 allows for higher system performance, easier-todesign clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device.

Embedded Core Features

■ Implemented in an ORCA Series 3 FPGA array.

■ Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer.

■ No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock, and a frame pulse.

■ High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.

■ HSI function uses Lucent Technologies Microelectronics Group’s proven 622 Mbits/s serial interface core.

■ Four-channel HSI function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 2.5 Gbits/s (full duplex).

■ LVDS I/Os compliant with EIA*-644, support hot insertion.

■ 8:1 data multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic.

■ On-chip phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T Recommendation G.958 (0.6 UIP-P at 250 kHz).

■ Powerdown option of HSI receiver on a perchannel basis.

■ Highly efficient implementation with only 3 overhead vs. 25 for 8B10B coding.

■ In-Band management and configuration.

■ Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.

■ Built-in boundry scan (IEEE? 1149.1 JTAG).

■ FIFOs align incoming data across all four channels for STS-48 (2.5 Gbits/s) operation (in quad STS-12 format).

■ 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications.