NDB6020P中文資料仙童半導體數(shù)據(jù)手冊PDF規(guī)格書

General Description

These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

Features

■ -24 A, -20 V. RDS(ON) = 0.05 W @ VGS= -4.5 V.

RDS(ON) = 0.07W @ VGS= -2.7 V.

RDS(ON) = 0.075 W @ VGS= -2.5 V.

■ Critical DC electrical parameters specified at elevated

temperature.

■ Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

■ 175°C maximum junction temperature rating.

■ High density cell design for extremely low RDS(ON).

■ TO-220 and TO-263 (D2PAK) package for both through

hole and surface mount applications.