N80C188EBXX中文資料英特爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

INTRODUCTION

Unless specifically noted, all references to the 80C186EB apply to the 80C188EB, 80L186EB, and 80L188EB. References to pins that differ between the 80C186EB/80L186EB and the 80C188EB/80L188EB are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.

The 80C186EB is the first product in a new generation of low-power, high-integration microprocessors. It enhances the existing 186 family by offering new features and new operating modes. The 80C186EB is object code compatible with the 80C186XL/80C188XL microprocessors.

■ Full Static Operation

■ True CMOS Inputs and Outputs

■ Integrated Feature Set

— Low-Power Static CPU Core

— Two Independent UARTs each with an Integral Baud Rate Generator

— Two 8-Bit Multiplexed I/ O Ports

— Programmable Interrupt Controller

— Three Programmable 16-Bit Timer/Counters

— Clock Generator

— Ten Programmable Chip Selects with Integral Wait-State Generator

— Memory Refresh Control Unit

— System Level Testing Support (ONCE Mode)

■ Direct Addressing Capability to 1 Mbyte

Memory and 64 Kbyte I/O

■ Speed Versions Available (5V):

— 25 MHz (80C186EB25/80C188EB25)

— 20 MHz (80C186EB20/80C188EB20)

— 13 MHz (80C186EB13/80C188EB13)

■ Available in Extended Temperature

Range (- 40°C to + 85°C)

■ Speed Versions Available (3V):

— 16 MHz (80L186EB16/80L188EB16)

— 13 MHz (80L186EB13/80L188EB13)

■ Low-Power Operating Modes:

—Idle Mode Freezes CPU Clocks but keeps Peripherals Active

—Powerdown Mode Freezes All Internal Clocks

■ Supports 80C187 Numeric Coprocessor

Interface (80C186EB PLCC Only)

■ Available In:

—80-Pin Quad Flat Pack (QFP)

—84-Pin Plastic Leaded Chip Carrier (PLCC)

—80-Pin Shrink Quad Flat Pack (SQFP)