N74F377AD中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書
N74F377AD規(guī)格書詳情
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
FEATURES
? High impedance inputs for reduced loading (20μA in Low and High states)
? Ideal for addressable register applications
? Enable for address and data synchronization applications
? Eight edge–triggered D–type flip–flops
? Buffered common clock
? See ’F273A for Master Reset version
? See ’F373 for transparent latch version
? See ’F374 for 3–State version
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
24+ |
3000 |
公司存貨 |
詢價(jià) | ||||
PHI |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量 |
詢價(jià) | ||||
PHILIPS/飛利浦 |
22+ |
DIP-20 |
9600 |
原裝現(xiàn)貨,優(yōu)勢(shì)供應(yīng),支持實(shí)單! |
詢價(jià) | ||
PIL |
21+ |
DIP2-0 |
10000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) | ||
PHILIPS/飛利浦 |
23+ |
SOP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
SOP |
20000 |
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢(shì)訂貨,價(jià)格優(yōu)勢(shì)、品種 |
詢價(jià) | ||
PIL |
2020+ |
DIP2-0 |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增 |
詢價(jià) | ||
NXP |
23+ |
PLCC |
8890 |
價(jià)格優(yōu)勢(shì)/原裝現(xiàn)貨/客戶至上/歡迎廣大客戶來(lái)電查詢 |
詢價(jià) | ||
PHILIPS/飛利浦 |
2022 |
SOP |
80000 |
原裝現(xiàn)貨,OEM渠道,歡迎咨詢 |
詢價(jià) | ||
PHIL |
1997 |
9000 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢價(jià) |
