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MT47H128M8CF-3EAT中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書
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DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
Features
? VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
? JEDEC-standard 1.8V I/O (SSTL_18-compatible)
? Differential data strobe (DQS, DQS#) option
? 4n-bit prefetch architecture
? Duplicate output strobe (RDQS) option for x8
? DLL to align DQ and DQS transitions with CK
? 8 internal banks for concurrent operation
? Programmable CAS latency (CL)
? Posted CAS additive latency (AL)
? WRITE latency = READ latency - 1 tCK
? Selectable burst lengths (BL): 4 or 8
? Adjustable data-output drive strength
? 64ms, 8192-cycle refresh
? On-die termination (ODT)
? Industrial temperature (IT) option
? Automotive temperature (AT) option
? RoHS-compliant
? Supports JEDEC clock jitter specification
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---|---|---|---|---|---|---|---|
MICRON |
2016+ |
FBGA |
6528 |
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詢價(jià) | ||
MICRON |
24+ |
N/A |
8000 |
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詢價(jià) | ||
Micron(鎂光) |
589220 |
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詢價(jià) | ||||
Micron |
24+ |
FBGA60 |
50000 |
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FBGA60 |
1256 |
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詢價(jià) | |||
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19+ |
BGA |
85966 |
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詢價(jià) | ||
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17+ |
BGA |
6200 |
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詢價(jià) | ||
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21+ |
BGA |
12588 |
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詢價(jià) | ||
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23+ |
BGA |
8000 |
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詢價(jià) | ||
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22+ |
FBGA |
10000 |
原裝正品優(yōu)勢(shì)現(xiàn)貨供應(yīng) |
詢價(jià) |