MPC5200BDS中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

Key features are shown below.

? MPC603e series e300 core

– Superscalar architecture

– 760 MIPS at 400 MHz (–40 oC to +85 oC)

– 16 KB Instruction cache, 16 KB Data cache

– Double precision FPU

– Instruction and Data MMU

– Standard and Critical interrupt capability

? SDRAM / DDR Memory Interface

– Up to 133 MHz operation

– SDRAM and DDR SDRAM support

– 256 MB addressing range per CS, two CS available

– 32-bit data bus

– Built-in initialization and refresh

? Flexible multi-function External Bus Interface

– Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices

– 8 programmable Chip Selects

– Non-multiplexed data access using 8-/16-/32-bit databus with up to 26-bit address

– Short or Long Burst capable

– Multiplexed data access using 8-/16-/32-bit databus with up to 25-bit address

? Peripheral Component Interconnect (PCI) Controller

– Version 2.2 PCI compatibility

– PCI initiator and target operation

– 32-bit PCI Address/Data bus

– 33 and 66 MHz operation

– PCI arbitration function

? ATA Controller

– Version 4 ATA compatible external interface—IDE Disk Drive connectivity

? BestComm DMA subsystem

– Intelligent virtual DMA Controller

– Dedicated DMA channels to control peripheral reception and transmission

– Local memory (SRAM 16 KB)

? 6 Programmable Serial Controllers (PSC)

– UART or RS232 interface

– CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97

– Full duplex SPI mode

– IrDA mode from 2400 bps to 4 Mbps

? Fast Ethernet Controller (FEC)

– Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface

? Universal Serial Bus Controller (USB)

– USB Revision 1.1 Host

– Open Host Controller Interface (OHCI)

– Integrated USB Hub, with two ports.

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