MN6153中文資料松下數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Overview

The MN6153UC is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data input.

It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump.

It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (0.5 mW for VDD=1.03 V, FIN= 60 MHz).

Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation.

Features

● Low power supply voltage: VDD=1.0 to 1.4V

● Low power consumption: 0.5mW (VDD=V1.03V, FIN=60MHz)

● High-speed operation: FIN=60MHz (VDD=1.03V)

● Frequency dividing ratios in reference frequency

● dividing stage: 5 to 131,071

● Frequency dividing ratios in comparator stage: 272 to 262,143

● Lock detector output pin

● Two types of phase comparator output

- Internal charge pump output

- Output for external charge pump

● Output monitor pins for both comparator and reference frequency dividing stages