ML6691中文資料MICRO-LINEAR數據手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/ decoder, a Stream Cipher scrambler/descrambler, and collision detect. Additional functions of the ML6691 — accessible through the two-wire MII management interface — include full duplex operation, loopback, power down mode, and MII isolation.

FEATURES

■ Conforms to the Fast Ethernet 100BASE-T IEEE 802.3μ standard

■ Integrated 4B/5B encoder/decoder

■ Integrated Stream Cipher scrambler/descrambler

■ Compliant MII interface

■ Two-wire serial interface management port for configuration and control

■ On-chip 25 MHz crystal oscillator

■ Interfaces to either AMD’s PDT/PDR (AM79865/79866) or Motorola’s FCG (MC68836)

■ Used with ML6673 for 100BASE-TX solutions

■ 44-pin PLCC package